Clock-Less Logic

Ms Bindiya M Varghese
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The speed of a computer in general refers to the number of times the system clock beats in unit period of time. Every action of the system is designed to work according to the rhythm of the processor clock. The long-established perception of synchronous design is now challenged by the proposition of elements like Muller-C or GasP. Paper starts with the discussion of benefits and decriments of synchronous design and how asynchronous design tries to overcome it. Paper continues with prologue to the different research that has been going on in this particular area.

Keywords: Asynchronous design, Muller-C, GasP, Micropipelines
Stream: Knowledge and Technology
Presentation Type: Virtual Presentation in English
Paper: A paper has not yet been submitted.

Ms Bindiya M Varghese

Lecturer, Rajagiri School of Computer Science, Rajagiri College of Social Sciences, Kalamassery, Kochi-683104,Kerala

Ref: T06P0158